1: Field of the Invention
The present Invention relates to a mask ROM and a method for manufacturing the mask ROM. More specifically, the present invention relates to a mask ROM in which spec (specification) can be switched to another spec on the basis of each ROM code by means of ion implantation.
2: Description of the Related Art
Each of the conventional mask ROMs is one of a semiconductor memory device, where data storage is performed by means of ion implantation in channel regions of transistors selected from a plurality of insulated gate transistors being arranged in a matrix form on a memory region by ROM code data which varies from one user to another. In addition, most of the conventional mask ROMs employ the following system.
In this system, that is, data is read out by generating internal control pulses from a delay circuit on the basis of standard pulses (reference pulses) generated from an ATD circuit (Address Transition Detecting circuit), for example as disclosed in Japanese Patent Application Laying-open No. 6-5079 (1994), formed on a region of a semiconductor substrate other than the memory region.
Hereinafter, we will describe the conventional mask ROM with reference to FIG. 1 to FIG. 3.
In FIG. 1, an ATD circuit system 90 comprised of a plurality of ATD circuits (Address Transition Detecting circuits) 91 receive each address signal 92 to generate a standard pulse 93.
Subsequently, a delay circuit system 80 receives the standard pulse 93 and also receives a signal 95 from a WCR circuit 94 that changes the width of a signal using the capacity of a transistor. Then the delay circuit system 80 generates an internal control signal pulse 81. The internal control signal 81 is used for controlling the operations of a SA (sense amp) circuit, an output circuit, and so on.
In the conventional mask ROM as shown in FIG. 1, however, the operation spec thereof is defined only by the standard pulse from the ATD circuit and the internal control signal pulse is then defined by such an ATD circuit. Therefore, the changing or relaxation of a selection spec does not correspond to the changing of the operation spec.
FIG. 2 is a flow chart for illustrating a method for manufacturing the conventional mask ROM. In this method, channel regions of transistors are selected using ROM code data which varies from one user to another. Then, an ion implantation is performed on such channel regions to control the threshold of the transistor to store DATA. After the step of data storage, the same post-process (the same aluminum wring process) is performed.
A user A requires ROM code data A and requires an internal control signal pulse for data rate (the speed at which data is generated) signal of 100 NS.
A user B requires ROM code data B and requires an internal control signal pulse for data rate (the speed at which data is generated) signal of 130 NS.
A mask ROM to be delivered to the user A forms a code reticle (reticle mask) for obtaining ROM code data A and performs ion implantation on channel regions of a group of transistors among a plurality of transistors being arranged in a matrix form on a memory region to alter the thresholds of these transistors.
A mask ROM to be delivered to the user B forms a code reticle for obtaining ROM code data B and performs ion implantation on channel regions of a group of transistors among a plurality of transistors being arranged in a matrix form on a memory region to alter the thresholds of these transistors.
Subsequently, the same aluminum wiring pattern is used for the wiring of each of the mask ROM to be delivered to the user A and the mask ROM to be delivered to the user B. In other words, wiring patterns of the respective mask ROMs are formed using the same aluminum reticle.
Then, both mask ROMs in FIG. 2 are constructed so as to obtain the same internal control signals from the circuit shown in FIG. 1.
In this case, the fabrication of each mask ROM should be conformity to 100 NS of one having a rate faster than another.
Consequently, each of the mask ROMs has the same internal control signal pulse, so that 100 NS products can be obtained regardless of same or different specs.
In some cases, however, the user B wants a 130 NS product having a data flow slower than that of 100 NS. Thus, the above pulse determination is strict with the user B who wants have a wider variety of specs to choose from.
Alternatively, as shown in FIG. 3, there is another method for manufacturing a conventional mask ROM comprising the different post-processes. In this method, a channel region of a transistor is selected using ROM code data which varies from one user to another. Then, an ion implantation is performed on such a channel to change the threshold of the transistor to store DATA. After the step of data storage, the different aluminum wring processes are performed for the respective users.
That is, in spite of using the same internal control signal pulse, the mask ROM to be delivered to the user A forms a wiring pattern using an aluminum reticle corresponding to spec of 100 NS and the mask ROM to be delivered to the user B forms a wiring pattern using an aluminum reticle corresponding to spec of 130 NS.
The aluminum reticle can be changed as described above, so that an appropriate aluminum reticle can be used depending on the need of the user. The product corresponding to each user, i.e., the product corresponding to the user B who may accept a slow data rate, is formed using its aluminum pattern. The production yields can be improved even though severe pulse setting can be applied. An appropriate post-process is individually applied on each user, so that the desired product can be satisfactory obtained.
In the conventional method shown in FIG. 3, however, a different aluminum reticle must be required for each user, so that the productivity is inevitably decreased by the increase of the number of different steps and the additional step for producing a different kind of the aluminum reticle.
Therefore, in the conventional method shown in FIG. 2, strict specifications are forced to any product that only require relaxed specifications, resulting -in the reduced yields.
In the conventional method shown in FIG. 3, on the other hand, at the time of performing an aluminum wiring after storing different ROM code data for each user""s application, a different aluminum reticle must be required for each user""s specifications, resulting in the reduced yields.
Therefore, an object of the present invention is to provide an effective mask ROM and a method for manufacturing such a mask ROM, where the resulting mask ROM allows the use of the same aluminum reticle for forming aluminum wiring pattern and also allows the fabrication of a product that corresponds to the specifications for each user even though ROM code data varies depending on the application being desired by the user and the specifications vary depending on the user.
A first aspect of the present invention is to provide a mask ROM where selective introduction of impurities is performed on a memory region, preferably a channel region of transistor in the memory region, formed on a semiconductor substrate on the basis of ROM code data supplied from a user, comprising: a specification switching means formed on a region of the semiconductor substrate other than the memory region, wherein the specification switching means is operative for selecting a specification by selective introduction of impurities on the basis of information about the specification supplied from the user.
Preferably, here, the mask ROM may further comprise a circuit for generating an internal control pulse by passing a standard pulse from an address transition detecting circuit through a delay circuit, so that a route for generating the internal control pulse from the standard pulse is changed using the specification switching means. In this case, the mask ROM may be further comprise: a first delay circuit, a second delay circuit, an inverter, a first NAND circuit, and second NAND circuit; a first route for providing the second NAND circuit with an input of a pulse obtained by passing a standard pulse from the address transition detecting circuit through the first delay circuit and an input of a fixed potential; and a second route for providing the first NAND circuit with an input of pulse obtained by passing a standard pulse from the address transition detecting circuit through the first delay circuit, the inverter, and the second delay circuit and an input of fixed potential, and for providing the second NAND circuit with an input of an output from the first NAND circuit and an input of a pulse obtained by passing a standard pulse from the address transition detecting circuit through the first delay circuit, wherein one of the first route and the second route is selected by the specification switching means.
Alternatively, the mask ROM may preferably further comprise a circuit for generating an internal control pulse by passing a standard pulse from the address transition detecting circuit through the delay pulse, so that the specification switching means is the change in the amount of delay in the delay circuit. In this case, the delay circuit may comprise a plurality of transistors to be provided as capacity elements, so that the amount of delay in the delay circuit can be defined by performing ion implantation on channel regions of the selected transistors.
In another aspect of the present invention is to provide a method for manufacturing a mask ROM, comprising the steps of: preparing a reticle mask that meats ROM code data and spec information provided from a user; performing ion implantation corresponding to the spec information on a semiconductor substrate when the ion implantation is selectively performed on the semiconductor substrate on the basis of the ROM code data.
Here, the ion injection depending on the ROM code data and the ion injection depending on the spec information may be preferably performed on a channel region of insulated gate field effect transistor.
Furthermore, the method may further comprise the step of wiring formation, which is performed after the step of ion implantation, or alternatively further comprise the step of wiring formation, which is performed before the step of ion implantation.